? semiconductor components industries, llc, 2004 december, 2004 ? rev. 3 1 publication order number: NUD3048/d NUD3048 fet switch 100 v, 800 m , n?channel, tsop?6 the NUD3048 provides a single device solution for a number of applications requiring a low power, high voltage, fet switch. the package includes a gate resistor and gate to source zener clamp. this switch can accommodate a wide range of input voltages, making it compatible with most current logic levels. its 100 v rating makes it compatible with 48 v telecom applications. features ? 100 v rating on gate 2 ? integrated 100 k r g option ? integrated esd diode protection ? low threshold voltage typical applications ? fet switch ? inverter ? level shifter ? inrush limiter ? relay driver figure 1. block diagram gate 2 6 100 k 13 gate 1 source drain 2, 4, 5 tsop?6 case 318g style 9 marking diagram 1 6 jw7 d jw7 = specific device code d = date code device package shipping 2 ordering information tsop?6 3000 / tape & reel NUD3048mt1 1 6 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. http://onsemi.com
NUD3048 http://onsemi.com 2 maximum ratings symbol rating value unit v dss drain to source v oltage continuous 100 v v g1ss gate to source voltage continuous @ 1.0 ma 15 v i d drain current continuous (t a =25 c) (note 1) (note 2) 0.7 1.2 a p d power dissipation (t a =25 c) (note 1) (note 2) 0.66 1.56 w v g2ss gate resistor to source voltage continuous 100 v t jmax maximum junction t emperature 150 c r ja thermal impedance (junction?to?ambient) (note 1) thermal impedance (junction?to?ambient) (note 2) 190 80 c/w esd human body model (hbm) class 2 machine model class a according to eia/jesd22/a114 specification 2000 100 v v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. electrical characteristics (t j =25 c unless otherwise noted.) characteristic symbol min typ max unit off characteristics drain to source leakage current (v ds = 80 v, v gs = 0 v) i dss ? 20 100 a gate body leakage current (v gs =10 v, v ds = 0 v) (v gs = 10 v, v ds = 0 v, t j = 125 c) i gss i gss ? ? 3.0 6.0 10 20 a on characteristics gate threshold voltage (i d = 1.0 ma) v gs 1.3 1.7 2.0 v drain to source resistance (v gs = 4.5 v, i d = 100 ma) r ds(on) ? 0.65 0.82 drain to source resistance (v gs = 10 v, i d = 100 ma) r ds(on) ? 0.6 0.72 dynamic characteristics input capacitance (v ds = 5.0 v, v gs = 0 v, f = 10 khz) c iss ? 135 ? pf output capacitance (v ds = 5.0 v, v gs = 0 v, f = 10 khz) c oss ? 75 ? pf transfer capacitance (v ds = 5.0 v, v gs = 0 v, f = 10 khz) c rss ? 26 ? pf gate bias characteristics gate resistor r g 75 100 125 k gate zener breakdown voltage (i z = 1.0 ma) (note 3) gate zener breakdown voltage (i z = 3.0 ma) (note 4) v z 15 100 17 115 ? ? v 1. min pad, 1 oz. cu. 2. 1 inch pad, 1 oz cu. 3. measured from gate 1 to source. 4. measured from gate 2 to source.
NUD3048 http://onsemi.com 3 figure 2. v ds(on) variation with i ds and gate voltage 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 i ds (a) v ds(on) (v) v gs = 2.0 v v gs = 3.0 v v gs = 5.0 v v gs = 7.0 v v gs = 10 v 0.55 0.60 0.65 0.70 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 figure 3. on resistance variation with drain current and gate voltage r ds(on) ( ) i d (a) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ?10 ?8 ?6 ?4 ?2 0246810 figure 4. variation of r ds(on) with temperature and gate voltage at i d = 100 ma i gs ( a) v gs (v) v gs = 4.5 v v gs = 10 v v gs = 4.5 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 ?50 0 50 100 150 figure 5. gate leakage current variation with gate voltage r ds(on) variation with temperature r ds(on) v gs = 4.5 v v gs = 10 v v gs = 4.5 v 0.5 6.00e?05 6.20e?05 6.40e?05 6.60e?05 6.80e?05 7.00e?05 7.20e?05 7.40e?05 ?40.0 ?20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 figure 6. variation of leakage current i dss (a) with v gs = 0 v and v ds = 100 v leakage current i ds s junction temperature i dss
NUD3048 http://onsemi.com 4 package dimensions tsop?6 case 318g?02 issue l style 9: pin 1. low voltage gate 2. drain 3. source 4. drain 5. drain 6. high voltage gate 0.95 0.037 1.9 0.075 0.95 0.037 mm inches scale 10:1 1.0 0.039 2.4 0.094 0.7 0.028 23 4 5 6 a l 1 s g d b h c 0.05 (0.002) dim min max min max inches millimeters a 0.1142 0.1220 2.90 3.10 b 0.0512 0.0669 1.30 1.70 c 0.0354 0.0433 0.90 1.10 d 0.0098 0.0197 0.25 0.50 g 0.0335 0.0413 0.85 1.05 h 0.0005 0.0040 0.013 0.100 j 0.0040 0.0102 0.10 0.26 k 0.0079 0.0236 0.20 0.60 l 0.0493 0.0610 1.25 1.55 m 0 10 0 10 s 0.0985 0.1181 2.50 3.00 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. m j k soldering footprint on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NUD3048/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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